Modern computer algorithms design photonic integrated circuits — light chips capable of separating signals by frequency (color) for spectroscopy. Unlike traditional engineering, light paths in these chips are not straight waveguides but chaotic, almost organic mazes. Such winding patterns, found by optimization algorithms, demonstrate high efficiency, but for a long time it remained a mystery which specific parts of the structure are critical for operation. Chip manufacturing inevitably involves microscopic deviations, and until now there was no way to predict where a tiny inaccuracy would lead to catastrophic failure, and where it would be harmless.

Researchers developed a method that brings clarity: an additional neural network, trained on simulation results, builds a sensitivity map over the design. This map visualizes the spatial distribution of the impact of manufacturing defects on output characteristics. Bright spots on it, like marks on a treasure map or hazards on a nautical chart, indicate areas where any deviation from the designed geometry is critical. Experimental verification on a real chip confirmed the predictions: deliberately damaging a "hot" spot increased optical losses (a photometric parameter) by 11 times more than identical damage in a zone marked as unimportant.

The proposed approach does not require rebuilding the complex simulation models used in design; it adds interpretability to their results. Designers get a tool to assess the technological robustness of a circuit before going into production, seeing in advance whether it will withstand the inevitable imperfections of lithography and etching. In the long run, this could accelerate the creation of reliable photonic chips needed in optical transceivers for new internet generations and in quantum computer interfaces.